1. Field of the Invention
The present invention relates to a semiconductor memory device and a semi-finished product for an integrated semiconductor device. More particularly, the present invention relates to a semiconductor memory device that allows an acceleration test such as a burn-in test, and a semi-finished product for an integrated semiconductor device that allows such testing in a wafer state prior to dicing.
2. Description of the Background Art
FIG. 39 is a block diagram schematically showing a structure of a memory cell and a row decoder widely used in a dynamic random access memory device (referred to as DRAM hereinafter). Referring to FIG. 39, a memory cell 111 includes an access transistor 112 and a cell capacitor 113, connected to a corresponding word line WL and a bit line BL. A row decoder selecting one word line in response to a row address signal includes a row predecoder 121a, a predecode signal line 122, and a plurality of word drivers. One word driver is provided corresponding to each word line WL. In FIG. 39, only one word driver WD is typically shown. Row predecoder 121a predecodes row address signals RA1-RA4 and complementary row address signals /RA1-/RA4 to generate predecode signals X1-X8 which are supplied to predecode signal line 122. Each word driver is activated in response to one of predecode signals X1-X4 and one of predecode signals X5-X8. When the word driver is rendered active, a boosted potential VPP higher than the power potential VPP higher than the power supply potential is supplied to a corresponding word line.
Word driver WD includes N channel MOS transistors 124 and 125 connected in series between a precharge node NX and a ground node, P channel MOS transistors 126 and 127 connected in parallel between a boosting node to which boosted potential VPP is supplied and precharge node NX, and a P channel MOS transistor 128 and an N channel MOS transistor 129 forming a CMOS inverter. During an inactive period of the DRAM (chip), a precharge signal PR of an L level (logical low) is applied to the gate electrode of transistor 126. In response, precharge node NX is precharged to an H level (logical high). Therefore, all the word lines are fixed to an L level when the chip is inactive. When the chip is activated, precharge signal PR is pulled up to an H level from an L level, whereby the precharge operation of node NX by transistor 126 is suppressed. However, word line WL maintains its L level since node NX is held at the H level. This is because the potential of word line WL is fed back to the gate electrode of transistor 127, whereby transistor 127 continuously supplies charge to node NX. Therefore, the charge of node NX must be discharged towards the ground node in order to render word line WL active. This word driver WD has both transistors 124 and 125 turned on when one predecode signal DECA out of predecode signals X1-X4 attains an H level and one predecode signal DECB out of predecode signals X5-X8 attains an H level. As a result, the potential of node NX is pulled down towards the L level, whereby transistors 128 and 129 are turned on and off, respectively. Thus, word line WL is activated, so that the potential thereof is boosted to the level of the boosted potential VPP.
FIG. 40 is a circuit diagram showing a structure of row predecoder 121a shown in FIG. 39. Referring to FIG. 40, row predecoder 121a includes NOR gates 1211-1218, inverters 1221a-1228a and 1231-1238. Each of NOR gates 1211-1214 receives either row address signal RA1 or a complementary row address signal /RA1, and either row address signal RA2 or a complementary row address signal /RA2. Each of NOR gates 1215-1218 receives either a row address signal RA3 or a complementary row address signal RA3, and either a row address signal RA4 or a complementary row address signal /RA4. Each of NOR gates 1211-1218 has its output signal provided to a word driver as a predecode signal via two inverters. For example, NOR gate 1211 receives row address signals /RA1 and /RA2 to provide predecode signal X1 to the word driver via two inverters 1221a-1231. Therefore, one of predecode signals X1-X4 attains an H level according to four combinations of row address signals RA1, /RA1, RA2, and /RA2. For example, predecode signal X1 attains an L level when row address signals /RA1 and /RA2 both attain an L level. Furthermore according to the four combinations of row address signals RA3, /RA3, RA4 and /RA4, one of predecode signals X5-X8 attains an H level. For example, when row address signals /RA3 and /RA4 both attain an L level, predecode signal X5 is pulled up to an H level.
In order to carry out a stress test on word line WL and access transistor 112 in the above-described DRAM, boosted potential VPP must be supplied to word line WL only during a predetermined time period. However, the testing is time-consuming according to increase in the capacity of a memory, resulting in increase in the cost required for testing. For example, a reliability test called xe2x80x9cburn-inxe2x80x9d that applies acceleration stress on a memory cell had a problem that the testing time period becomes longer as the number of memory cells becomes greater. The stress testing on a gate oxide film in access transistor 112 and on a dielectric film in cell capacitor 113 are extremely important. However, the number of word lines n that can be activated at one time is limited in a normal operation. Therefore, the testing must be carried for N (total number of word lines) /n times in order to evaluate all the word lines. The time required for testing becomes longer in accordance with a higher integration density of a chip.
A method of increasing the number of word lines that are activated simultaneously is considered as one way of reducing the testing time. An example of an DRAM that allows testing by such a method is shown in FIG. 41. FIG. 41 is substantially identical to FIG. 3 in pp. 639-642 of xe2x80x9cIEDM93, DIGESTxe2x80x9d. Referring to FIG. 41, the DRAM includes a memory cell array 11 having a plurality of word lines WL and bit lines (not shown) crossing thereto, a row decoder 12 selecting one of word lines WL, a column decoder 13 selecting one bit line, and a plurality of N channel MOS transistors 1 connected corresponding to word lines WL. Row decoder 12 includes a plurality of word drivers WD, each driving a corresponding word line WL. All transistors 1 are turned on in response to one multi-selection signal MLT, whereby boosted test potential VST is supplied to all word lines WL. Therefore, stress can be applied to all the access transistors simultaneously since all the word lines are activated in a burn-in mode. Thus, the testing time can be shortened.
FIG. 42 shows a semiconductor (silicon) wafer 70 not yet subjected to a dicing process. A plurality of semiconductor chips 71 are formed on silicon wafer 70. A probe card 2 as shown in FIG. 43 is used in carrying out an acceleration test such as burn-in on the wafer shown in FIG. 42. Probe card 2 includes an opening 3 corresponding to a plurality of chips 71 aligned in one row in the vertical direction (three in FIG. 42) in wafer 70. A plurality of probes 4 are provided corresponding to the three chips 71 at the periphery of opening 3. This probe card 2 is set on wafer 70 to carry out a burn-in test in a wafer state. Probes 4 are brought into contact with the pads (not shown) of the three chips 71, so that power supply and a signal for testing can be applied simultaneously to the three chips 71. In order to test all the chips 71 in wafer 70, the setting position of probe card 2 must be shifted 5 times.
Since boosted test potential VST is supplied to word line WL via transistor 1 in the DRAM of FIG. 41, boosted test potential VST must be higher than boosted potential VPP by the threshold voltage of transistor 1 in order to supply a boosted potential VPP higher than the power supply potential to word line WL. Therefore, a great stress is applied on transistor 1 controlled by multi-selection signal MLT which is greater than that on the access transistor that should actually receive the greater stress. As a result, there is a possibility that these transistors 1 become defective. Furthermore, since one transistor 1 must be provided corresponding to each word line WL, reduction in the pitch between word lines WL due to miniaturization of the chip is attributed to the difficulty of forming a transistor with such small pitches. As a result, there is a possibility that these transistors 1 become defective.
When silicon wafer 70 as shown in FIG. 42 is to be tested using probe card 2 shown in FIG. 43, the setting position of probe card 2 must be changed 5 times with respect to wafer 70. There was a problem that the entire testing of wafer 70 was time consuming.
In view of the foregoing, one object of the present invention is to provide a semiconductor memory device of a simple structure that allows acceleration testing by activating a plurality of word lines simultaneously.
Another object of the present invention is to provide a semi-finished product for an integrated semiconductor device that allows acceleration testing in a wafer state at a short time period.
According to an aspect of the present invention, a semiconductor memory device can be operated in a normal mode and a test mode. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a plurality of drive circuits, and an activation circuit. The plurality of bit lines cross the word lines. The plurality of memory cells are provided corresponding to respective crossings of a word line and a bit line. Each memory cell is connected to a corresponding word line and bit line. The plurality of drive circuits are provided corresponding to the word lines. Each drive circuit drives a corresponding word line. The activation circuit selectively activates one drive circuit in response to an externally applied row address signal when in a normal mode, and activates at least two drive circuits in response to a predetermined multi-selection signal and independent of a row address signal in a test mode.
The above semiconductor memory device has one drive circuit selectively activated in response to an externally applied row address signal in a normal mode, whereby a corresponding word line is driven. In a test mode, at least two drive circuits are activated in response to a predetermined multi-selection signal and independent of a row address signal in a test mode, whereby at least two word lines are driven. Thus, the testing time is shortened.
According to another aspect of the present invention, a semiconductor memory device can be operated in a normal mode and a test mode. The semiconductor memory device includes a plurality of word line groups, a plurality of bit lines, a plurality of memory cells, a plurality of drive circuits, and an activation signal. Each word line group includes a plurality of word lines. The plurality of word lines cross a word line. The plurality of memory cells are provided corresponding to respective crossings of a word line and a bit line. Each memory cell is connected to a corresponding word line and a bit line. The plurality of drive circuits are provided corresponding to the word lines. Each drive circuit drives a corresponding word line. The activation circuit selectively activates one drive circuit in response to an externally applied row address signal when in a normal mode, and activates all the drive circuits corresponding to one word line group in response to a plurality of multi-selection signals supplied corresponding to a word line group when in a test mode.
The above-described semiconductor memory device has one drive circuit selectively activated in response to an externally applied row address signal when in a normal mode, whereby a corresponding one word line is driven. When in a test mode, all the word lines in one word line group are driven in response to multi-selection signals in a test mode. Therefore, a testing in which word lines are driven in a divisional manner can be carried out.
According to a further aspect of the present invention, a semiconductor memory device includes a semiconductor substrate, a plurality of word lines, plurality of bit lines, a plurality of memory cells, a plurality of drive circuits, an activation circuit, a substrate potential supply circuit, a cell plate potential generation circuit, and a cell plate potential supply circuit. The plurality of word lines are formed on a semiconductor substrate. The plurality of bit lines are formed on the semiconductor substrate crossing the word lines. The plurality of memory cells are provided corresponding to respective crossings of a word line and a bit line. Each memory cell includes a cell capacitor and an access transistor. The cell capacitor is formed on the semiconductor substrate, and includes a cell plate and a storage node to store data. The access transistor includes a gate electrode, and one and the other source/drain regions. The gate electrode is formed on the semiconductor substrate, and is connected to a corresponding word line. One source/drain region is formed in the semiconductor substrate, and is connected to a corresponding bit line. The other source/drain region is formed in the semiconductor substrate, and is connected to the storage node of a cell capacitor. The plurality of drive circuits are provided corresponding to the word lines. Each drive circuit drives a corresponding word line. The activation circuit selectively activates one drive circuit in response to an externally applied row address signal when in a normal mode, and activates at least two drive circuits in response to a predetermined multi-selection signal regardless of a row address signal when in a test mode. The substrate potential supply circuit responds to multi-selection signal to selectively supply a predetermined substrate potential and a predetermined first test potential to the semiconductor substrate. The cell plate potential generation circuit generates a cell plate potential for a cell plate. The cell plate potential supply circuit selectively supplies a cell plate potential from the cell plate potential generation circuit and a predetermined second test potential to the cell plate in response to the multi-selection signal.
According to still another aspect of a semiconductor memory device of the present invention, one word line is activated and a predetermined substrate potential is supplied to a semiconductor substrate in response to an externally applied row address signal when in a normal mode, whereby a cell plate potential from a cell plate potential generation circuit is supplied to a cell plate. In a test mode, a first test potential is supplied to the semiconductor substrate, and the second test potential is supplied to the cell plate. The first test potential is supplied to a storage node via the other source/drain region of the access transistor. Therefore, a predetermined voltage can be applied to the cell capacitor of a memory cell.
According to a still further aspect of the present invention, a nonvolatile semiconductor memory device can be operated in a normal mode and a data erasure mode. The nonvolatile semiconductor memory device includes a plurality of word lines, a plurality of source lines, a plurality of floating gate type memory cells, a plurality of drive circuits, and an activation circuit. The plurality of source lines cross the word lines. The plurality of floating gate type memory cells are provided corresponding to respective crossings of a word line and a source line. Each floating gate type memory cell is connected to a corresponding word line and a source line. The plurality of drive circuits are provided corresponding to the word lines. Each drive circuit drives a corresponding word line. The activation circuit selectively activates one drive circuit in response to an externally applied row address signal when in a normal mode, and activates at least two drive circuits in response to a predetermined multi-selection signal and independent of an address signal in a data erasure mode.
The above-described nonvolatile semiconductor memory device has one drive circuit activated in response to an externally applied row address signal in a normal mode, whereby a corresponding one word line is driven. In a test mode, at least two drive circuits are activated in response to a multi-selection signal, whereby at least two word lines are activated. Therefore, data written in floating gate type memory cells can partially be erased.
According to yet another aspect of the present invention, a semi-finished product for an integrated semiconductor device includes a semiconductor wafer, a plurality of semiconductor chips, and a first test interconnection. The plurality of semiconductor chips are formed on the semiconductor wafer to attain a test mode in response to an external test signal provided from the outside world. The first test interconnection is provided on the semiconductor wafer and formed in a region other than the region where the plurality of semiconductor chips are located. The first test interconnection is connected in common to the plurality of semiconductor chips, and receives an external test signal.
In the above-described semi-finished product for an integrated semiconductor device, the first test interconnection is formed on a dicing region of a semiconductor wafer in which a plurality of semiconductor chips are formed. An external test signal is applied to all the semiconductor chips via the first test interconnection. Since all the semiconductor chips attain a test mode, the testing time under a wafer state can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.